Memtest86+ Adds ARM64 Support and DDR5 Stress Testing

Memtest86+ has expanded beyond its traditional x86 stronghold, introducing native support for ARM64 platforms alongside a suite of new diagnostic tools designed to expose hardware faults that increasingly plague modern DDR5 systems.

The open-source memory tester now boots on AArch64 machines running UEFI and ACPI. Early validation covers Qualcomm Snapdragon X laptops, Raspberry Pi 4 and 5 boards flashed with community UEFI firmware, and QEMU virtual environments. This shift reflects the broader migration of Windows PCs and enterprise servers toward ARM silicon, where pre-boot hardware diagnostics have historically lagged behind the mature x86 ecosystem.

DDR5 instability drives much of the architectural overhaul in this release. High-density modules rely on onboard Power Management Integrated Circuits (PMICs) rather than motherboard voltage regulation, introducing new failure vectors. A newly implemented bus stress test targets these vulnerabilities by rapidly alternating between write-bursts and read-checks while inserting deliberate idle periods. These load transitions stress the module’s PMIC in ways that on-die Error Correcting Code cannot mask, exposing signal integrity failures caused by electrical noise or voltage drops. The sequence specifically hunts for training errors tied to aggressive XMP and EXPO overclocking profiles, which frequently cause system crashes that standard operating-system-level diagnostics fail to isolate.

To push memory bandwidth further during testing, older random-sequence routines have been rewritten using SIMD instructions. Combined with non-temporal stores that bypass CPU caches entirely, these tests write directly to main memory, generating significantly higher traffic than scalar operations.

Security researchers will note the inclusion of an updated Rowhammer test. Modern DIMMs employ Target Row Refresh (tRR) to neutralize classic double-sided hammer attacks. Memtest86+ counters this mitigation using Blacksmith-style patterns derived from 2022 academic research. By applying non-uniform, multi-sided access synchronized with DRAM refresh cycles, and inferring row layout through access timing via a DRAMA-lite approach, the tool can still trigger bit flips. Detected Rowhammer errors are logged but intentionally excluded from BadRAM masking patterns, as they represent physical security vulnerabilities rather than standard defective cells.

Hardware identification has also hardened. The software now verifies the checksum and CRC of Serial Presence Detect (SPD) data across DDR5, DDR4, and legacy modules. Corrupted SPD data frequently causes motherboards to hang during POST, yet most diagnostic utilities ignore it. Modules failing this check are explicitly flagged. On locked-down OEM laptops and ARM boards where the SMBus is inaccessible, the program falls back to SMBIOS tables to retrieve module size, type, speed, and model numbers. Recognition databases have grown by over 100 new DRAM brands, and platform support extends to upcoming architectures like Intel Wildcat Lake.

For technicians managing hardware at scale, the utility now operates headlessly. Passing the log= boot parameter generates machine-parsable serial output for every event, including system information, pass progress, and specific errors. A maxpasses= option allows automated restart after a set number of cycles, enabling integration into continuous integration build systems and test lab environments. Users requiring physical documentation can press F6 during execution to write a numbered, full-text report containing system and module details to a FAT32-formatted USB drive, preventing accidental overwrites of previous logs.

Low-level improvements address long-standing stability issues, including fixes for random hangs in x2APIC SMP mode and more accurate CPU temperature reporting on AMD EPYC server platforms. The bit fade test now fills every DRAM cell with random data while forcing adjacent neighbors to carry opposite charges, verified simultaneously across all available CPU cores.

Memtest86+ continues to operate independently of any underlying operating system or UEFI libraries, booting directly via legacy BIOS, UEFI, or intermediate bootloaders supporting Linux 16-bit, 32-bit, 64-bit, or EFI handover protocols. It remains compatible with any Pentium-class or newer processor.