Samsung Unveils Next-Gen zHBM and 400-Layer 3D Memory to Power AI Data Centers

SANTA CLARA, Calif. — Samsung Electronics Co. unveiled next-generation high-bandwidth memory and 3D storage architectures designed for artificial intelligence infrastructure, pushing processing speeds higher as global memory makers redirect production capacity toward high-margin data center demand.

At the Future of Memory and Storage conference in Santa Clara, the South Korean semiconductor maker introduced concept models for zHBM, an advanced 3D memory structure that directly stacks High Bandwidth Memory vertically above AI accelerators rather than placing chips side by side. Samsung said the vertical integration delivers up to eight times the performance of traditional layouts and utilizes next-generation wafer bonding to increase memory density by more than ten times over HBM5 technology while improving power efficiency threefold.

Samsung also showcased its V10 BV-NAND storage technology featuring more than 400 stacked memory cell layers. The bonding architecture raises memory bit density by 58% over the company’s V9 generation while enhancing read, write, and input/output capabilities across enterprise server drives and mobile memory.

For edge computing and localized artificial intelligence tasks, Samsung introduced zNAND-O, a compact storage architecture emphasizing low latency and high bandwidth efficiency. The firm also demonstrated LPDDR5X-PIM, the industry’s first mobile low-power memory built with processing-in-memory technology, designed to handle computational tasks directly inside the memory chip to reduce power consumption.

Samsung and rival SK Hynix control the vast majority of global DRAM and NAND flash supply. As both memory giants prioritize chip supplies for hyperscale data center operators, constrained supply for standard memory chips continues to exert upward pressure on consumer technology pricing across laptops, smartphones, and hardware devices worldwide.