Chip Giants Plot Radical Mask Revolution to Unlock AI Chip Potential

VELHOVEN, Netherlands — ASML Holding NV and the world’s leading semiconductor manufacturers are laying the groundwork for a massive, industry-wide overhaul of chip-printing technology to prevent next-generation lithography tools from bottlenecking the production of giant artificial intelligence processors.

At the heart of the issue is the physical limit of how much circuitry can be printed on a silicon wafer in a single step. Today’s standard EUV machines utilize a 0.33 numerical aperture lens to print chip patterns up to a standard reticle limit of approximately 800 square millimeters. This exposure field is large enough to print the massive graphics processing units (GPUs) and AI accelerators designed by companies like Nvidia Corp. and Alphabet Inc.’s Google in a single exposure.

However, ASML’s next-generation High-NA EUV systems—the Twinscan EXE series—increase the numerical aperture to 0.55 to print much finer circuit patterns. To achieve this higher resolution without requiring excessively large mirror angles that would cause light-shading errors, ASML introduced anamorphic optics. These specialized lenses magnify the chip design by 4x in one direction and 8x in the other, which effectively cuts the exposure field size in half (to about 420 square millimeters) when using standard 6-inch masks.

The Dutch photolithography monopoly is collaborating with its customers and supply chain partners to transition to a new 12-inch (300-millimeter) photomask format for its upcoming High Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) systems. This shift, targeted for high-volume manufacturing by 2033, aims to solve a fundamental physical constraint of High-NA tools that threatens the economic viability of manufacturing oversized chips designed for AI data centers and cloud infrastructure.

To print an 800-square-millimeter AI chip using current High-NA configurations, chipmakers must perform “stitching”—printing the design in two separate exposures and precisely joining them together on the silicon wafer. Stitching slows down production, risks alignment errors, and increases manufacturing costs, making the highly anticipated machines, which cost upwards of $350 million each, less economically attractive for the largest logic chips.

“If we’re going to pull it off as an industry, then you’ll actually see that the productivity of those systems will go up by 40%,” ASML Chief Technology Officer Marco Pieters told Reuters.

Retooling the industry for 12-inch masks is a monumental task that requires cooperation far beyond ASML itself. The transition requires a coordinated ecosystem overhaul, affecting manufacturers of mask blanks, pellicles (the protective membranes that shield masks from dust), inspection systems, and mask-writing equipment.

By doubling the physical size of the photomask to 12 inches, ASML and its partners can restore a full-sized exposure field for High-NA machines, eliminating the need for stitching on large chips.

Because of these complex logistics, the industry is pursuing a multi-stage timeline. ASML expects to demonstrate a pilot line utilizing the larger 12-inch masks in 2031, with full commercial readiness slated for 2033.

In the interim, chipmakers are mapping out their early adoption of High-NA tools using existing 6-inch mask formats. Intel Corp., which took early delivery of the first commercial High-NA tool, is currently utilizing the technology for development work, targeting laptop processors and its advanced 14A node.

Other key players are taking a more cautious approach to volume production for logic chips. Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest contract chipmaker, has indicated it expects to introduce High-NA EUV into high-volume manufacturing of its advanced-node chips starting in 2030.

Memory chipmakers Samsung Electronics Co. and SK Hynix Inc. are targeting 2028 to begin utilizing High-NA EUV for mass production of high-density dynamic random-access memory (DRAM) chips. South Korea’s SK Hynix also stated that it is currently evaluating whether to join the industry consortium working to establish the 12-inch mask standard.

The joint development effort underscores the shifting economics of advanced semiconductor manufacturing. While EUV lithography, which uses 13.5-nanometer wavelength light, has been essential for printing sub-7-nanometer chips since the late 2010s, the escalating costs of High-NA systems require maximum wafer throughput to justify their adoption. Enabling larger exposure fields is critical to broadening the appeal of the equipment, ensuring that the industry can scale both the density of its transistors and the physical size of its most powerful silicon.